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LANS Informal Seminar: Sri Hari Krishna Narayanan
March 25, 2009 @ 15:00 CDT
Seminar Title: Process Variation Aware Thread Mapping for Chip Multiprocessors
Speaker: Sri Hari Krishna Narayanan, MCS
Date/Time: 2009-03-25 15:00
Location: Building 221, Room A216
Description:
With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This talk considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency.